module led(Clock, E, Data, Q);
	parameter n = 8;
	input [n:0] Data;
	input E, Clock;
	output reg [n:0] Q;
	
	initial begin
		Q <= 0;
	end
	
	always @(posedge Clock) begin
		if (E == 1)
			Q <= Data;
	end
endmodule
